JANUARY 2026
ANALOG AND DIGITAL ELECTRONICS
Time Allowed: 2.5 Hours Full Marks: 60
Answer to Question No. 1 of Group A must be written in the main answer script. In Question No. 1, out of 2 marks for each MCQ, 1 mark is allotted for right answer and 1 mark is allotted for correct explanation of the answer.
Answer any Five (05) Questions from Group-B.
GROUP-A
1. Choose the correct answer from the given alternatives and explain your answer (any ten): 2×10=20
i. Ripple frequency of the output waveform of a full wave rectifier when fed with a 50 Hz sine wave is –
- a) 25 Hz
- b) 50 Hz
- c) 100 Hz
- d) 200 Hz
Show Answer
Answer: c) 100 Hz
Explanation: A full-wave rectifier produces two output pulses for every cycle of the input sine wave. Therefore, the ripple frequency is twice the input frequency: 2 × 50 Hz = 100 Hz.
ii. When the positive voltage on the gate of a p-channel JFET is increased, its drain current-
- (a) increases
- (b) decreases
- (c) remains the same
- (d) none of the mentioned
Show Answer
Answer: (b) decreases
Explanation: For a p-channel JFET, making the gate more positive relative to the source increases reverse bias of the gate-channel junction. This reduces the magnitude of drain current.
iii. Need of BJT biasing to.
- (a) Ensure BJT to be at saturation region
- (b) ensure maximum efficiency
- (c) stabilize the operating point
- (d) reduce heating effect.
Show Answer
Answer: (c) stabilize the operating point
Explanation: BJT biasing establishes a suitable operating point in the active region and helps keep it stable against variations in temperature and transistor parameters.
iv. What is the main role of DAC?
- a) convert analog signal to digital signal
- b) convert digital signal to analog signal
- c) amplify signal
- d) rectify signal
Show Answer
Answer: b) convert digital signal to analog signal
Explanation: A digital-to-analog converter (DAC) converts a digital binary code into a corresponding analog voltage or current.
v. Value of intrinsic stand – off ratio of UJT is
- (a) 0 – 0.5
- (b) 0.5
- (c) 0.5 – 1
- (d) 1
Show Answer
Answer: (c) 0.5 – 1
Explanation: The intrinsic stand-off ratio η of a UJT is normally between 0.5 and 1. It is determined by the resistive division of the interbase resistance.
vi. Zener diode is a _____ doped device.
- (a) heavily
- (b) lightly
- (c) moderately
- (d) zero
Show Answer
Answer: (a) heavily
Explanation: A Zener diode is heavily doped so that its depletion region is very thin and controlled breakdown can occur at a specified reverse voltage.
vii. For sustained oscillation, which one is true according to Barkhausen criteria:-
- (a) |Aβ| > 1
- (b) |Aβ| = 1
- (c) |Aβ| < 1
- (d) |Aβ| = ∞
Show Answer
Answer: (b) |Aβ| = 1
Explanation: For sustained oscillations, the magnitude of loop gain must be unity and the total phase shift around the loop must be 0° or an integral multiple of 360°. Thus |Aβ| = 1.
viii. PIV for a diode in a bridge rectifier is
- (a) Vₘ
- (b) 2Vₘ
- (c) Vₘ/2
- (d) Vₘ/4
Show Answer
Answer: (a) Vₘ
Explanation: In a bridge rectifier, each non-conducting diode is subjected to a peak inverse voltage equal to the peak value of the transformer secondary voltage, Vₘ.
ix. The code used for levelling cells of K-map is
- (a) BCD
- (b) octal
- (c) Hexadecimal
- (d) grey
Show Answer
Answer: (d) grey
Explanation: Karnaugh maps arrange adjacent cells using Gray code so that neighboring cells differ in only one binary variable.
x. In a S-R flip flop if Q̅ = 0, output is said to be
- (a) set
- (b) reset
- (c) previous state
- (d) no change.
Show Answer
Answer: (a) set
Explanation: In the conventional S-R flip-flop terminology, Q̅ = 0 means Q = 1, which is the set state.
xi. Which one is correct for odd parity transmission –
- (a) data 1101 000, parity 1
- (b) data 1001 000, parity 0
- (c) data 1101 000, parity 0
- (d) data 1101 000, parity 1
Show Answer
Answer: (a) data 1101 000, parity 1
Explanation: The data 1101000 contains four 1s, which is even. Adding a parity bit of 1 makes the total number of 1s five, which is odd.
xii. A RAM which can collect data for both positive and negative edge of clock pulse is called –
- (a) Static RAM
- (b) Dynamic RAM
- (c) SD RAM
- (d) DDR RAM
Show Answer
Answer: (d) DDR RAM
Explanation: DDR RAM transfers data on both the rising and falling edges of the clock. This doubles the data-transfer rate compared with single-data-rate memory at the same clock frequency.
xiii. The number of control lines required for 16 to 1 multiplexer –
- (a) 1
- (b) 2
- (c) 3
- (d) 4
Show Answer
Answer: (d) 4
Explanation: A 16-to-1 multiplexer has 16 input lines, so the number of select/control lines required is log₂16 = 4.
xiv. How many flip flops are required to make MOD-13 counter –
- (a) 2
- (b) 3
- (c) 4
- (d) 5
Show Answer
Answer: (c) 4
Explanation: The number of flip-flops n must satisfy 2ⁿ ≥ 13. Since 2³ = 8 and 2⁴ = 16, four flip-flops are required.
xv. The output of sequential circuit depends on-
- a) present input only
- b) past output only
- c) both present input and past output
- d) past output only
Show Answer
Answer: c) both present input and past output
Explanation: A sequential circuit has memory, so its output depends on the present input as well as the previous state or past output.
GROUP-B
Answer any Five (05) questions.
2. (a) What is α, β and γ of transistor? (b) Find out the relation between α and β of transistor. (c) If base current of a transistor is 30μA when the emitter current is 7.2mA, what are the values of α & β? [3+2+3]
3. (a) Define (i) drain resistance, (ii) transconductance and (iii) amplification factor of JFET. (b) When a reverse voltage of 10V is applied between gate and source of JFET, the gate current is 0.1μA. Find resistance between gate and source. [(3×2)+2]
4. (a) What is tank circuit of oscillator? (b) Mention the Barkhausen criterion of oscillator. (c) With diagram explain the operation of Wien bridge oscillator. [2+2+4]
5. (a) State difference between avalanche and zener breakdown. (b) Define rectifier efficiency and ripple factor of full wave diode bridge rectifier circuit. (c) Explain the operation of series inductive filter circuit. [2+(2+2)+2]
6. (a) Explain binary full subtractor using truth table, logic expressions and logic gate diagram. (b) Develop a half subtractor circuit using universal gate. [5+3]
7. Design (any two) (a) Decimal to BCD encoder (b) Single bit magnitude comparator (c) odd parity generator. [4+4]
8. (a) With diagram explain the operation of 4 bit asynchronous down counter. (b) Sketch the diagram of 4 bit ring counter and draw the output waveforms of it. [4+(2+2)]
9. (a) Explain principle of operation of Successive approximation method A/D converter with relevant diagrams. (b) Write down the operating principle of R-2R ladder D/A using suitable diagrams. [4+4]
11. Write short note (any four) (a) Memory access, (b) DDR RAM, (c) EEPROM, (d) propagation delay, (e) noise immunity. [2×4]